1. Field of the Invention
This invention relates to high resolution analog-to-digital converters (ADCs), and more particularly to resettable high order delta-sigma ADCs.
2. Description of the Related Art
Analog-to-digital converters (ADCs) and their counterpart digital-to-analog converters (DACs) are an important class of electrical systems. They are ubiquitous in electrical circuits, having applications ranging from automotive systems to advanced communication systems. Just as the name conveys, ADCs accept a continuous analog signal and convert it to a discrete digital signal. DACs perform the reverse operation. A good ADC recreates an analog signal digitally while maintaining the integrity of the original signal and limiting information loss to an acceptable level.
Several different design approaches have been utilized to realize ADC circuitry, such as flash converters, single- and dual-slope integrating converters, and tracking converters. Each of these designs offers various advantages over the others. Some important characteristics of ADCs include resolution, conversion rate or speed, and step recovery. Resolution is the number of binary bits output by the converter. Speed is a measure of how fast the converter can output a new binary number. In discrete time systems and digital signal processing, bandwidth is associated with the sampling rate, and the term is often used to describe the speed of such a system. Step recovery is a measure of how fast a converter can react in response to a large, sudden jump in the input signal.
A great deal of research and design work has been done to achieve a high-bandwidth, high-resolution ADC. This is a challenge as these two characteristics are inversely related. A high-resolution output requires large amounts of data to be processed, increasing system process time and thus decreasing bandwidth. Advances in the area of high-bandwidth, high-resolution ADCs have been made in some systems such as GaAs and InP; however, these systems require a great deal more power than do systems using silicon, for example.
One area of technology driving the development of faster ADCs is high-speed high-resolution imaging. CMOS image sensor processes have led to very small devices having all of the imager components on a single chip. See Joshi et al., “Scalable Architecture for High-Resolution Video-Rate CMOS Imaging System On Chip,” 2005 IEEE Workshop on CCDs and Advanced Image Sensors, pp. 181-185, 2005. The detector, the pixel multiplexer, the column processors can all be implemented on the same silicon using these advanced processes. As a result, there are several high quality cost-efficient camera systems on the market today.
Current state-of-the-art imagers digitize image data to 10-12 bits of resolution at 10 s of mega samples per second (MSPS). Recent scientific, industrial and aerospace applications demand higher resolution at even higher output rates. New ADC technologies are needed to satisfy these high-speed requirements. Pipeline converters have been the choice of digitization in imaging applications, because they are realized in a standard CMOS process. They have moderate resolution and can be operated at video rates. The current trend in imaging is moving toward higher resolution at higher frame rates. A parallel array of pipeline converters can provide the desired rates at the expense of increased complexity and power. These applications require low-power high-resolution ADCs that work well in the digital environment.
One solution is to use high-order parallel delta-sigma (Δ-Σ) converters. The circuitry for these converters is relatively simple, but they require oversampling the input to reduce errors and noise. Δ-Σ converters usually assume a band-limited input. The converter decimation filters use the band-limited input assumption and previous output values to predict a current value. However, for imaging applications, correlation between samples is not acceptable. Array-based sensor applications often have uncorrelated pixel data either due to the type of the application (high MTF requirement) or due to the readout scheme (e.g., a single channel reading nonadjacent channels successively).
Each sample coming out of a sensor readout circuit is a step input to a Δ-Σ converter. Using the classical Δ-Σ approach would result in the loss of current data due to some residual memory of the previous sample. This problem may be addressed by resetting the ADC for each input in a first-order system. FIG.1 illustrates a known first-order resettable Δ-Σ converter. A resettable first-order Δ-Σ ADC is presented in C. Jansson, “A High-Resolution, Compact, and Low-Power ADC Suitable for Array Implementation in Standard CMOS”, IEEE Transactions on Circuits and Systems-I: Fund. Thoery and App., vol. 42, pp. 904-912, November 1995. However, first-order systems require high oversampling ratios to achieve high accuracy. Their applications are limited to in-pixel conversions or low-accuracy, low-power parallel readout schemes. Recently, the order of a resettable system has been increased to a second-order system. See S. A. Paul et al., “A Nyquist-Rate Pipelined Oversampling A/D Converter”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1777-1787, December 1999; R. Harjani et al., “FRC: A Method for Extending the Resolution of Nyquist Rate Converters Using Oversampling”, IEEE Transactions on Circuits and Systems-II, Vol. 45, No. 4, pp. 482-494, April 1998.